A frequency synthesizer is an apparatus that generates an output signal having a frequency that is an exact multiple of a reference frequency. The accuracy of the output signal frequency is typically determined by the accuracy and stability of the reference frequency source.
A common type of frequency synthesizer uses a phase-locked loop (PLL) to provide an output signal having a selectable, precise and stable frequency. The PLL includes a phase detector, a voltage-controlled oscillator (VCO) and a feedback path arranged in a way that the phase of the VCO output is forced to be synchronous with the phase of the input reference frequency. FIG. 1 is a circuit diagram showing a configuration of a conventional integer-N phase locked loop (PLL) circuit having an integer frequency divider.
Referring to FIG. 1, a frequency divider 10 generates a reference clock signal Refclk by dividing the frequency of a reference signal Fosc by N. A phase-frequency comparator (PFD) 11 receives the reference clock signal Refclk and a feedback signal Fbclk, which is obtained by dividing an output signal Fvco of a voltage controlled oscillator (VCO) 14 by a frequency divider 15. The phase-frequency comparator 11 detects a phase error between the reference clock signal Refclk and the feedback signal Fbclk, and outputs pulse signals UP and DN corresponding to the phase error. A charge pump 12 generates a charge pump output current in response to the pulse signals UP and DN. The charge pump output current flows to a loop filter 13. The loop filter 13 removes a high frequency constituent of the charge pump output current, and outputs a control signal in proportion to the inputted current. The VCO 14 generates the output signal Fvco in proportion to the control signal of the loop filter 13. The output signal Fvco is divided by M, or, multiplied by 1/M, by the frequency divider 15, and is fed back to the phase-frequency comparator 11 as the feedback signal Fbclk. Accordingly, the output signal Fvco can be described as follows:Fvco=Refclk*M=Fosc* (M/N)
Therefore, the integer-N PLL circuit can obtain the output signal Fvco having a frequency that is M/N times higher than that of the reference signal Fosc. By using a divider circuit in the VCO feedback path and controlling the division ratio, a variable frequency can be provided at the output of the frequency synthesizer. In this manner, the VCO output frequency is an exact multiple of the reference frequency. In other words, Fvco tracks the frequency of the reference signal Fosc.
However, in an integer-N PLL, the requirement of frequency resolution normally obtained by the pre-divider become incompatible with jitter requirements which dictate loop bandwidth necessary to suppress VCO noise. The finer the frequency resolution or channel spacing directs the loop bandwidth to be very low, whereas the lower jitter requirements dictate the loop bandwidth to be relatively high.
Fractional-N PLL's are employed trying to address the drawbacks of integer-N PLL. There are three basic approaches to implementing a fractional-N PLL. At the heart of all the approaches is a multi-modulus feedback counter that is directed to implement a time-averaged fractional division of the output frequency when compared to the reference frequency. FIG. 2 shows a classical fractional-N approach. A fixed pattern of divide by M and M+1 is used to effect the time averaged fractional division. For instance, in order to generate an output frequency that is 200.1 times the reference frequency, a M/M+1 divider 25 is provided in the feedback look to divide the output signal Fvco by 200 for 9 reference cycles and by 201 for one reference cycle. This gives a time-average of (9*200+201)/10=200.1 times the reference frequency. Under normal operation using a fractional pattern, a phase error will accumulate while the feedback counter 25 divides the output signal Fvco by M, and the phase error is reduced or removed when the counter 25 divides the output signal Fvco by M+1. FIG. 3 shows changes of phase errors during different dividing processes. However, the operation of fractional-N PLL usually causes in-band frequency spurs as shown in FIG. 4, which manifests itself in output jitter and is undesirable. To suppress spurs in the classical fractional-N PLLs, the only recourse is to reduce the loop bandwidth, which would result in more VCO noise.
Other modified types of fractional-N PLL also were proposed to improve the performance of PLLs, such as PLLs using DAC compensation to minimize phase errors introduced by the classical fractional-N, or fractional-N PLL using delta-sigma approach, wherein the loop filter has a sharper transition band to reject the out of band noise introduced by the modulator used in conventional fractional-N PLLs.
For the DAC compensation approach, although the spurs can be lowered, it is a purely open-loop method and relies on accuracy of the compensation. Consequently, the spurs can only be reduced to a finite level of maybe −20 dBc. The delta-sigma approach, though can remove fractional-spurs, needs to deal with different problems arising from the unique design of the delta-sigma approach. For instance, in delta-sigma modulators, idle tones are introduced as in-band spurs at very low frequencies. These tones can be removed by adding dither, which, however, would add design complexity to an already complex system. Although higher order modulators can be used to reduce the idle tone generation by increasing the chaotic energy which busts up the tonal energy, higher order modulators require steeper transition loop filters which in turn affect phase margin and stability. MASH delta-sigma architectures have been introduced to remove the problem of instability. However, the MASH delta-sigma approach suffers from similar tonal problems. Dithering may be employed to suppress the tonal generation but this introduces more complexity into an already complex system.
Therefore, there is a need for a PLL that can effectively reduce the phase errors introduced by the operation of the PLL. Additionally, there is another need for a PLL design with minimal complexity and efficient phase-error reductions.